1. Technical Field of the Invention
The present invention relates an improved sense amplifier with feedback-controlled bitline access.
2. Description of Related Art
The sense amplifier circuit shown in FIG. 1 represents a common sense amplifier topology used in SRAM and DRAM cells. The function of a sense amplifier in a DRAM is to amplify the signal and to restore the levels on the bit lines to their full logic levels since the read operation in a one-transistor cell is destructive. In SRAMs, the use of a sense amplifier offers performance enhancements. The sense amplifier can be used to speed up memory access since the bit lines do not have to swing to their full value by discharging through the cell. Additionally, the sense amplifier transistors can be made quite large compared to the cell transistors to drive the bit lines to full logic level quickly.
A sense amplifier amplifies the data signals in either a normal mode or an altered mode. In the normal mode, the data signals must be complementary to each other. Conversely, while in the altered mode, the data signals need not be complementary to each other. In the normal mode, a mode control circuit couples each of the data signals to a respective second input of each sense amplifier so that each sense amplifier receives complimentary data signals at its differential inputs. In the altered mode, the mode control circuit couples a reference voltage to the second inputs of the sense amplifier in the first stage so that each sense amplifiers compares a respective data signal to the reference voltage. Normal mode sense amplifiers are commonly used for high speed SRAM's. Access to the bitline is provided to the evaluating nodes. The sense amplifier enable signal is used for initiating latching operation and disconnecting the bitlines during the evaluation phase.
FIG. 1 shows the schematic circuit diagram of a conventional normal mode latch type sense amplifier. The circuit consists of p-type MOS transistors M11, M12 and n-type MOS transistors M13, M14 connected such that they form a data latch. The data latch is provided with an enabling/disabling MOS transistor M15. When the MOS transistor M15 is enabled, it provides a path to the power supply to complete the circuit.
The data latch is accessed by bitlines BL and BLB through MOS transistors M16 and M17. MOS transistors M15, M16 and M17 are provided with a control signal, sense amplifier enable (SAEN), at their gates such that when the access MOS transistors M16 and M17 are enabled MOS transistor M15 remains disabled and vice versa. Signal nodes SN1 and SN2 are the evaluating nodes of the latch. A MOS transistor M18 is connected between nodes SN1 and SN2 of the latch. The gate of M18 is connected to Sense Amplifier Equalizing (SAEQ) signal. After wordline selection, one of the bitlines discharges through the memory cell. When a sufficient amount of voltage split (difference) is available at the latch evaluating nodes SN1 and SN2, signal SAEN disables access transistors M16 and M17 and thereby disconnects the bitlines from the evaluating nodes, while at the same time enabling transistor M15 provides a ground path for the latching operation.
In a conventional sense amplifier, undesired noise is generated at the sense amplifier nodes when the accessed device is switched off through the sense amplifier enable signal. Also, the input nodes of a conventional sense amplifier are disconnected to the bitlines during the evaluation stage, which disables the additional load on sense amplifier nodes due to charge injection from the bit lines. Noise generated at the sense amplifier nodes delays the evaluation.